Today's integrated circuits include a vast number of devices. Smaller devices are key to enhance performance and to improve reliability. As FET (Field-Effect-Transistor) devices are being scaled down, the technology becomes more complex. There is great difficulty in maintaining performance improvements in devices of deeply submicron generations. Several avenues are being explored for keeping device performance improvements on track Along the path of seeking ever higher device performances, downscaling of FET devices is the established guiding principle for current CMOS device technology. However, there are visible limits to straightforward downsizing as, among other issues, short-channel effects (SCE) become a major problem when devices are scaled down to the nanometer regime. A proposed way out of this problem is the use of double gated devices. Such a device is not simply a planar structure conducting on one surface, but conducting on two sides of the device body. The reasons that a double gate device can be downscaled further than a regular planar device are relatively complex, but they have been already given in the technical literature, for instance in: “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation,” by H.-S. P. Wong, et al, 1998 IEDM Tech Dig., pp. 407-10.
A variation of the double gated device is the so called FinFET device. In finFETs, the body of the transistor is formed in a vertical structure. The gate of the FinFET is engaging the vertically oriented body on both faces, or sides. FinFETs have several advantages, such as better SCE and are promising extensions of the mainline semiconductor technology. In general FinFET devices and manufacturing is tied in with semiconductor-on-insulator (SOI), usually meaning silicon-on-insulator technology. SOI devices, either customary planar ones, or vertically oriented ones, are fabricated in a thin semiconductor layer disposed over an insulator layer. Most commonly, the insulator layer is a so called buried oxide layer on a silicon (Si) substrate. There is a trend toward fabricating the planar FETs in ever thinner SOI layers, thereby increasing performance. State of the art planar SOI devices have so called fully depleted bodies, meaning lacking mobile charge carriers in the body, except for those induced by the gate electrode in the channel. FinFET devices typically have fully depleted bodies, as well, due to the narrowness of the vertically oriented structure. Also, the advantages of having gates on opposing sides of the vertically oriented body are more pronounced when the body is fully depleted between the two faces that are engaged by the gate electrode.
One of the disadvantages that FinFET devices have is that all the FinFET device widths are the same because the device width is determined by the height of the Fin. The uniformity of device widths places difficult constrains on circuit designs.